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general description the MAX31865 is an easy-to-use resistance-to-digital converter optimized for platinum resistance temperature detectors (rtds). an external resistor sets the sensitivity for the rtd being used and a precision delta-sigma adc converts the ratio of the rtd resistance to the reference resistance into digital form. the MAX31865s inputs are protected against overvoltage faults as large as q 50v. programmable detection of rtd and cable open and short conditions is included. applications industrial equipment medical equipment instrumentation features s simple conversion of platinum rtd resistance to digital value s handles 100 ? to 1k ? (at 0c) platinum rtds (pt100 to pt1000) s compatible with 2-, 3-, and 4-wire sensor connections s conversion time: 21ms max s 15-bit adc resolution; nominal temperature resolution 0.03125 n c (varies due to rtd nonlinearity) s total accuracy over all operating conditions: 0.5 n c (0.05% of full scale) max s 50v input protection s fully differential v ref inputs s fault detection (open rtd element, rtd shorted to out-of-range voltage, or short across rtd element) s spi-compatible interface s 20-pin tqfn package typical application circuits typical application circuits continued at end of data sheet. 19-6478; rev 0; 10/12 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX31865.related . MAX31865 bias refin+ dvdd v dd gnd1 gnd2 dgnd refin- drdy isensor sdi sclk host interface cs sdo n.c. force- r ref rtd r cable r cable 0.1f v dd force+ force2 rtdin+ rtdin- c i * r cable r cable 0.1f v dd 4-wire sensor connection *c i = 10nf for 1k rtd 100nf for 100 rtd MAX31865 rtd-to-digital converter evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com.
MAX31865 rtd-to-digital converter 2 voltage range on v dd relative to gnd1 ............ -0.3v to +4.0v voltage range on bias, refin+, refin-, isensor ................................. -0.3v to (v dd + 0.3v) voltage range on force+, force2, force-, rtdin+, rtdin- relative to gnd1 .... -50v to +50v voltage range on dvdd relative to dgnd ........ -0.3v to +4.0v voltage range on all digital pins relative to dgnd ............................. -0.3v to (v dvdd + 0.3v) continuous power dissipation (t a = +70 n c) tqfn (derate 34.5mw/ n c above +70 n c) ............... 2758.6mw esd protection (all pins, human body model) ................... 2kv operating temperature range ........................ -40 n c to +125 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c soldering temperature (reflow) ...................................... +260 n c lead temperature (soldering,10s) ................................. +300 n c tqfn junction-to-ambient thermal resistance ( q ja ) .......... 29c/w junction- to-case thermal resistance ( q jc ) ................. 2c/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) recommended dc operating conditions (t a = -40 n c to +125 n c, unless otherwise noted.) (notes 2 and 3) electrical characteristics (3.0v p v dd p 3.6v, t a = -40 n c to +125 n c, unless otherwise noted. typical values are t a = +25 n c, v dd = v dvdd = 3.3v.) (notes 2 and 3) parameter symbol conditions min typ max units v dd v dd 3.0 3.3 3.6 v dvdd v dvdd 3.0 3.3 3.6 v input logic 0 v il cs , sdi, sclk -0.3 0.3 x v dvdd v input logic 1 v ih cs , sdi, sclk 0.7 x v dvdd v dvdd + 0.3 v analog voltages (force+,force2, force-, rtdin+, rtdin-) normal conversion results 0 v bias v reference resistor r ref 350 10k i cable resistance r cable per lead 0 50 i parameter symbol conditions min typ max units adc resolution no missing codes 15 bits adc full-scale input voltage (rtdin+ - rtdin-) refin+ - refin- v maxim integrated
MAX31865 rtd-to-digital converter 3 electrical characteristics ( continued ) (3.0v p v dd p 3.6v, t a = -40 n c to +125 n c, unless otherwise noted. typical values are t a = +25 n c, v dd = v dvdd = 3.3v.) (notes 2 and 3) parameter symbol conditions min typ max units adc common-mode input range 0 v bias v input leakage current rtdin+, rtdin-, 0 n c to +70 n c, on-state 2 na rtdin+, rtdin-, -40 n c to +85 n c, on-state 5 rtdin+, rtdin-, -40 n c to 100 n c, on-state 14 bias voltage v bias 1.95 2.00 2.06 v bias voltage output current i out 0.2 5.75 ma bias voltage load regulation i out p 5.75ma 30 mv/ma bias voltage startup time (note 4) 10 ms adc full-scale error 1 lsb adc integral nonlinearity differential input, endpoint fit, 0.3 x v bias p v ref p v bias 1 lsb adc offset error -3 +3 lsb noise (over nyquist bandwidth) input referred 150 f v rms common-mode rejection 90 db 50/60hz noise rejection fundamental and harmonics 82 db temperature conversion time (note 5) t conv continuous conversion (60hz notch) 16.7 17.6 ms single conversion (60hz notch) 52 55 single conversion (50hz notch) 62.5 66 continuous conversion (50hz notch) 20 21 automatic fault detection cycle time from cs high to cycle complete 550 600 f s power-supply rejection 1 lsb/v power-supply current (note 6) i dd shutdown bias off, adc off 1.5 3 ma i dd bias on, active conversion 2 3.5 ma power-on reset voltage threshold 2 2.27 v power-on reset voltage hysteresis 120 mv input capacitance c in logic inputs 6 pf input leakage current i l logic inputs -1 +1 f a output high voltage v oh i out = -1.6ma v dvdd - 0.4 v output low voltage v ol i out = 1.6ma 0.4 v maxim integrated
MAX31865 rtd-to-digital converter 4 note 2: all voltages are referenced to ground when common. currents entering the ic are specified positive. note 3: limits are 100% production tested at t a = +25c and/or t a = +85c. limits over the operating temperature range and rel - evant supply voltage range are guaranteed by design and characterization. typical values are not guaranteed. note 4: for 15-bit settling, a wait of at least 10.5 time constants of the input rc network is required. max startup time is calculated with a 10k reference resistor and a 0.1f capacitor across the rtd inputs. note 5: the first conversion after enabling continuous conversion mode takes a time equal to the single conversion time for the respective notch frequency. note 6: specified with no load on the bias pin as the sum of analog and digital currents. no active communication. if the rtd input voltage is greater than the input reference voltage, then an additional 400a i dd can be expected. note 7: all timing specifications are guaranteed by design. note 8: measured at v ih = 0.7v x v dvdd or v il = 0.3 x v dvdd and 10ms maximum rise and fall times. note 9: measured with 50pf load. note 10: measured at v oh = 0.7 x v dvdd or v ol = 0.3 x v dvdd . measured from the 50% point of sclk to the v oh minimum of sdo. ac electrical characteristics: spi interface (3.0v p v dd p 3.6v, t a = -40 n c to +125 n c, unless otherwise noted. typical values are t a = +25 n c, v dd = v dvdd = 3.3v.) (notes 3 and 7) ( figure 1 and figure 2 ) parameter symbol conditions min typ max units data to sclk setup t dc (notes 8, 9) 35 ns sclk to data hold t cdh (notes 8, 9) 35 ns sclk to data valid t cdd (notes 8, 9, 10) 80 ns sclk low time t cl (note 9) 100 ns sclk high time t ch (note 9) 100 ns sclk frequency t clk (note 9) dc 5.0 mhz sclk rise and fall t r , t f (note 9) 200 ns cs to sclk setup t cc (note 9) 400 ns sclk to cs hold t cch (note 9) 100 ns cs inactive time t cwh (note 9) 400 ns cs to output high-z t cdz (notes 8, 9) 40 ns address 01h or 02h decoded to drdy high t drdyh after rtd register read access (note 9) 50 ns maxim integrated
MAX31865 rtd-to-digital converter 5 figure 1. timing diagram: spi read data transfer figure 2. timing diagram: spi write data transfer cs sclk sdi sdo t cc t cdh a7 a6 a0 d7 d6 d1 d0 t dc t cdd t cdd t cdz note: sclk can be either polarity , timing shown for cpol = 1. write address byte read data byte sclk sdi note: sclk can be either polarity , timing shown for cpol = 1. write address byte write data byte t cc t cdh t ch t r t f t cch t cwh t cdh a7 a6 a0 d7 d0 t dc t cl cs maxim integrated
6 typical operating characteristics (v dd = v dvdd = 3.3v, t a = +25c, unless otherwise noted.) adc conversion error vs. rtd resistance (400 r ref , 4-wire connection) MAX31865 toc06 r rtd ( ) error () 300 250 200 150 100 50 -0.244 0 0.244 ? 0.1c error 0.488 -0.488 0 350 +25c -40c +100c adc conversion error vs. rtd resistance (4k r ref , 4-wire connection) MAX31865 toc05 r rtd ( ) error () 3000 2500 2000 1500 1000 500 -0.244 0 0.244 ? 0.1c error 0.488 -0.488 0 3500 +25c -40c +100c sinc filter operation input frequency vs. noise response MAX31865 toc04 input noise frequency (hz) noise response (db) 130 90 50 -80 -60 -40 -20 0 20 -100 10 170 60hz 50hz leakage current per pin vs. temperature (1 volt applied to force+, force2, rtdin+, rtdin- pins) MAX31865 toc03 temperature (c) current (na) 125 100 75 20 40 60 80 100 120 140 0 50 150 supply current vs. temperature (adc normally off mode) MAX31865 toc02 temperature (c) i dd (ma) 100 50 0 1 2 3 4 0 -50 150 analog i dd (bias pin unloaded) digital i dd supply current vs. temperature (adc auto conversion mode) MAX31865 toc01 temperature (c) i dd (ma) 100 50 0 1 2 3 4 0 -50 150 analog i dd (bias pin unloaded) digital i dd MAX31865 rtd-to-digital converter maxim integrated
MAX31865 rtd-to-digital converter 7 pin configuration pin description pin name function 1 bias bias voltage output (v bias ) 2 refin+ positive reference voltage input. connect to bias. connect the reference resistor between refin+ and refin-. 3 refin- negative reference voltage input. connect the reference resistor between refin+ and refin-. 4 isensor low side of r ref. connect to refin-. 5 force+ high-side rtd drive. connect to force2 when using the 3-wire connection configuration. protected to q 50v. 6 force2 positive input used in 3-wire only. when in the 3-wire connection configuration, connect to force+. when in the 2-wire or 4-wire connection configuration, connect to ground. protected to q 50v. 7 rtdin+ positive rtd input. protected to q 50v. 8 rtdin- negative rtd input. protected to q 50v. 9 force- low-side rtd return. protected to q 50v. 10 gnd2 analog ground. connect to gnd1. 11 sdi serial-data input 12 sclk serial-data clock input 13 cs active-low chip select. set cs low to enable the serial interface. 14 sdo serial-data output MAX31865 tqfn (5mm x 5mm) top view 19 20 ep + 18 17 7 6 8 refin+ isensor force+ 9 bias sdo sclk sdi dgnd 12 drdy 45 15 14 12 11 dvdd v dd force- rtdin- rtdin+ force2 refin- cs 3 13 n.c. 16 10 gnd2 gnd1 maxim integrated
MAX31865 rtd-to-digital converter 8 pin description (continued) block diagram pin name function 15 dgnd digital ground 16 gnd1 analog ground. connect to gnd2. 17 n.c. do not connect 18 drdy active-low push-pull data-ready output. drdy goes low when a new conversion result is available in the data register. when a read-operation of an rtd resistance data register occurs, drdy returns high. 19 dvdd digital supply voltage input. connect to a 3.3v power supply. bypass to dgnd with a 0.1 f f bypass capacitor. 20 v dd analog supply voltage input. connect to a 3.3v power supply. bypass to gnd1 with a 0.1 f f bypass capacitor. ep exposed pad (bottom side of package). connect to gnd1. data registers vbias generator digit al logic serial logic bias v dd v dd v dvdd refin+ refin- isensor force+ force2 rtdin+ force- rtdin- dvdd sclk sdo sdi cs drdy dgnd 3-wire only 50/60hz digital sinc filter adc state machine digital comparator for fault detection master-initiated fault-detection cycle 15-bit ? adc MAX31865 gnd1 50v protection gnd2 maxim integrated
MAX31865 rtd-to-digital converter 9 detailed description the MAX31865 is a sophisticated rtd-to-digital converter with a built-in 15-bit analog-to-digital converter (adc), input protection, a digital controller, an spi-compatible interface, and associated control logic. the signal conditioning circuitry is optimized to work with pt100 through pt1000 rtds. thermistors are also supported. temperature conversion resistance temperature detectors (rtds) are sensors whose resistance varies with temperature. platinum is the most common, most accurate wire material; platinum rtds are referred to as pt-rtds. nickel, copper, and other metals may also be used to make rtds. characteristics of platinum rtds include a wide temperature range (to over +800 n c), excellent accuracy and repeatability, and reasonable linearity. for pt-rtds, the most common values for nominal resistance at 0 n c are 100 i and 1k i , though other values are available. the average slope between 0 n c and +100 n c is called alpha ( ). this value depends on the impurities and their concentrations in the platinum. the two most widely used values for alpha are 0.00385 and 0.00392, corresponding to the iec 751 (pt100) and sama standards. the resistance vs. temperature curve is reasonably linear, but has some curvature, as described by the callendar-van dusen equation: r(t) = r 0 (1 + at + bt 2 + c(t - 100)t 3 ) where: t = temperature ( n c) r(t) = resistance at t r 0 = resistance at t = 0 n c iec 751 specifies = 0.00385055 and the following callendar-van dusen coefficient values: a = 3.90830 x 10 -3 b = -5.77500 x 10 -7 c = -4.18301 x 10 -12 for -200 n c p t p 0 n c, 0 for 0 n c p t p +850 n c figure 3 shows the curve of resistance vs. temperature for a pt100 rtd along with a straight-line approximation based on the slope between 0 n c and +100 n c. to measure the rtds resistance, connect a reference resistor (r ref ) and rtd in series and apply the bias voltage to the top of r ref as shown in the typical application circuits . the reference resistor current also flows through the rtd. the voltage across the reference resistor is the reference voltage for the adc. the voltage across the rtd is applied to the adcs differential inputs (rtdin+ and rtdin-). the adc therefore produces a digital output that is equal to the ratio of the rtd resistance to the reference resistance. a reference resistor equal to four times the rtds 0 n c resistance is optimum for a platinum rtd. therefore, a pt100 uses a 400 i reference resistor, and a pt1000 uses a 4k i reference resistor. a 2-wire connection (see the typical application circuits ) can give acceptable results when the rtd is located close to the MAX31865. note that, for a pt100, series resistance of 0.4 i causes an error of approximately 1 n c. therefore, as the cable length increases, the error due to cable resistance can become excessive. the 4-wire connection eliminates errors due to cable resistance by using separate force and sense leads. a 3-wire connection is a compromise approach that uses one less conductor than the 4-wire approach. to compensate for the voltage drop across the return wire, the voltage between force+ and rtdin+ is subtracted from (rtdin+ - rtdin-). this is accomplished using the force2 sampling input. if the cable resistances are well-matched, the error due to cable resistance is cancelled. select 3-wire operation by setting the 3-wire bit in the configuration register to 1. figure 3. pt100 rtd resistance vs. temperature. pt100 rtd resistance vs. temperature temperature (c) resistance () 700 600 400 500 0 100 200 300 -100 50 100 150 200 250 300 350 400 450 0 -200 straight-line approximation rtd resistance maxim integrated
MAX31865 rtd-to-digital converter 10 linearizing temperature data for a temperature range of -100 n c to +100 n c, a good approximation of temperature can be made by simply using the rtd data as shown below: temperature ( n c) (adc code/32) C 256 this equation gives 0 n c error at 0 n c, -1.75 n c error at -100 n c, and -1.4 n c error at +100 n c (assuming an iec751 rtd and r ref equal to four times the 0 n c rtd resistance). for high precision, use the callendar-van dusen equation (in the temperature conversion section) or a lookup table to correct the rtds predictable nonlinearity. using thermistors other resistive sensors, such as thermistors (ntcs or ptcs) may be used. select an r ref that is greater than or equal to the sensors maximum resistance over the temperature range of interest. the output data is the ratio of the sensor resistance to the reference resistance. analog-to-digital converter (adc) the adc has fully differential analog inputs, rtdin+ and rtdin-, and fully differential reference inputs, refin+ and refin-. the output code represents the ratio between the analog input voltage and the reference voltage. a negative input voltage produces an output code of 0. an input voltage greater than the reference voltage produces a full-scale output. input noise is attenuated by a third-order digital sinc filter. noise from 50hz or 60hz power sources (including harmonics of the ac powers fundamental frequency) is attenuated by 82db. fault detection and input protection the MAX31865 detects a variety of faults that can occur with the external rtd and 2-, 3-, or 4-wire cables. some faults are detected on every conversion, while others are detected only when a fault detection cycle is requested by the master. during a fault detection cycle the MAX31865 has the ability to disconnect the force- input from its gnd2 return path by means of and internal analog switch. the conditions that generate a fault are listed below, see figure 4 for a fault detection flowchart. ? detected at any point in time overvoltage (> v dd ) or undervoltage (< gnd1) con - dition on force+, force2, rtdin+, rtdin-, or force- pins ? detected every adc conversion greater than or equal to threshold high conversion result less than or equal to threshold low conversion result ? detected on demand by initiating a fault detection cycle (configuration register bits (d[3:2]) v refin - > 0.85 x v bias v refin - < 0.85 x v bias when force- input switch is open v rtdin - < 0.85 x v bias when force- input switch is open force+, force2, force-, rtdin+, and rtdin- are protected against input voltages up to q 50v. signals applied to these pins are gated by analog switches that open when the applied voltage is typically greater than v dd + 100mv or less than gnd1 - 400mv. note that when a voltage fault occurs, the protection circuits may allow approximately 350 f a of current flow. this fault- induced leakage current does not cause any damage to the MAX31865. when an overvoltage or undervoltage condition is detected, bit d2 of the fault status register is set and the adc halts conversion updates until the fault is no longer detected, at which point conversions resume. maxim integrated
MAX31865 rtd-to-digital converter 11 figure 4. fault detection flowcharts master-initia ted f aul t -detection cycle - automa tic mode master-initia ted f aul t -detection cycle - manual mode n is force+, force2, force-, rtdin+, rtdin-, pins > v dd or < gnd protect pins against 50v y set bit d2 of fault status register adc halts updates set bit d0 of rtd data lsb register ever y conversion fa ul t detection monitor pins al wa ys active fa ul t detection f aul t detection master writes 100x010xb to configuration register nn is vrefin- > 0.85 x vbias 100s delay force-input switch remains closed open force- input switch force-input switch closed configuration register set to 100x000xb to end fault detection cycle is vrefin- < 0.85 x vbias is rtdin- < 0.85 x vbias n set bit d5 of fault status register set bit d0 of rtd data lsb register 100s delay 100s delay 210s delay y set bit d4 of fault status register set bit d0 of rtd data lsb register y set bit d3 of fault status register set bit d0 of rtd data lsb register y y 100s delay open force- input switch master writes 100x100xb to configuration register n is vrefin- > 0.85 x vbias 100s delay force-input switch remains closed did master write 100x110xb to configuration register 100s delay 100s delay y set bit d5 of fault status register set bit d0 of rtd data lsb register n is vrefin- < 0.85 x vbias set bit d4 of fault status register set bit d0 of rtd data lsb register y n force-input switch closed configuration register set to 100x000xb to end fault detection cycle is rtdin- < 0.85 x vbias n set bit d3 of fault status register set bit d0 of rtd data lsb register y perform conversion nn is rtd resistance value > high threshold register y set bit d7 of fault status register is rtd resistance value < low threshold register conversion initiated y set bit d6 of fault status register set bit d0 of rtd data lsb register maxim integrated
MAX31865 rtd-to-digital converter 12 internal registers communication is through eight 8-bit registers that contain conversion, status, and configuration data. all programming is done by selecting the appropriate address of the desired register location. table 1 illustrates the addresses for the registers. the registers are accessed using the 0xh addresses for reads and the 8xh addresses for writes. data is read from or written to the registers msb first. configuration register (00h) the configuration register selects the conversion mode (automatic or triggered by the 1-shot command), enables and disables bias pin output voltage v bias , initiates 1-shot conversions, selects the rtd connection (either 3-wire or 2-wire/4-wire), initiates a full fault detection cycle, clears the fault status register, and selects the filter notch frequencies. the effects of the configuration bits are described below. bias (d7) when no conversions are being performed, v bias may be disabled to reduce power dissipation. write 1 to this bit to enable v bias before beginning a single (1-shot) conversion. when automatic (continuous) conversion mode is selected, v bias remains on continuously. conversion mode (d6) write 1 to this bit to select automatic conversion mode, in which conversions occur continuously at a 50/60hz rate. write 0 to this bit to exit automatic conversion mode and enter the normally off mode. 1-shot conversions may be initiated from this mode. 1-shot (d5) when the conversion mode is set to normally off, write 1 to this bit to start a conversion. this causes a single resistance conversion to take place. the conversion is triggered when cs goes high after writing a 1 to this bit. note that if a multibyte write is performed, the conversion is triggered when cs goes high at the end of the transaction. if v bias is on (as selected by the configuration register), the rtd voltage is sampled when cs goes high and the conversion begins. note that if v bias is off (to reduce supply current between conversions), any filter capacitors at the rtdin inputs need to charge before an accurate conversion can be performed. therefore, enable v bias and wait at least 10.5 time constants of the input rc network plus an additional 1ms before initiating the conversion. note that a single conversion requires approximately 52ms in 60hz filter mode or 62.5ms in 50hz filter mode to complete. 1-shot is a self-clearing bit. table 1. register addresses and por state table 2. configuration register definition register name read address (hex) write address (hex) por state read/write configuration 00h 80h 00h r/w rtd msbs 01h 00h r rtd lsbs 02h 00h r high fault threshold msb 03h 83h ffh r/w high fault threshold lsb 04h 84h ffh r/w low fault threshold msb 05h 85h 00h r/w low fault threshold lsb 06h 86h 00h r/w fault status 07h 00h r d7 d6 d5 d4 d3 d2 d1 d0 v bias 1 = on 0 = off conversion mode 1 = auto 0 = normally off 1-shot 1 = 1-shot (auto-clear) 3-wire 1 = 3-wire rtd 0 = 2-wire or 4-wire fault detection cycle control (see table 3) fault status clear 1 = clear (auto-clear) 50/60hz filter select 1 = 50hz 0 = 60hz maxim integrated
MAX31865 rtd-to-digital converter 13 3-wire (d4) write 1 to this bit when using a 3-wire rtd connection. in this mode the voltage between force+ and rtdin+ is subtracted from (rtdin+ - rtdin-) to compensate for the ir errors caused by using a single wire for the force- and rtdin- connections. when using 2-wire or 4-wire connections, write 0 to this bit. fault detection cycle (d3:d2) the master initiated fault detection cycle has two modes of operation, manual and automatic mode timing. if the external rtd interface circuitry includes an input filter with a time constant greater than 100 f s, the fault detection cycle timing should be controlled in the manual mode operation. the fault detection cycle checks for three faults by making the following voltage comparisons and setting the associated bits in the fault status register: 1) is the voltage at refin- greater than 85% x v bias ? (fault status register bit d5) 2) is the voltage at refin- less than 85% x v bias when force- input switch is open? (fault status register bit d4) 3) is the voltage at rtdin- less than 85% x v bias when force- input switch is open? (fault status register bit d3) note: all voltages are referenced to gnd1. the applications information provides tables for decoding possible causes of set fault status bits. to enter the automatic fault detection cycle, write 100x010xb to the configuration register. the adc is now in normally off mode. the automatic fault detection cycle inserts 100 f s delays before checking for faults, thereby allowing the external input filter to settle. the fault detect cycle bits (d[3:2]) self-clear to 00b upon completion. to enter the manual fault detection cycle, first ensure that v bias has been on for at least 5 time constants. next, write 100x100xb to the configuration register. the adc is now in normally off mode. the MAX31865 checks for faults while the force- input switch is closed, and when the check completes, the force-input switch opens. the fault detect cycle bits (d[3:2]), remain set to 10b. again, wait at least 5 time constants, and then write 100x110xb to the configuration register. the MAX31865 now checks for faults while the force- inputs switch is open; when the check completes, the force- input switch closes and the fault detect cycle bits (d[3:2]) self-clear to 00b. note that if 1 is written to d5 (1-shot) and d2 or d3 in a single write, both commands are ignored. if 100x110xb is set without a prior initiation of the first manual step (setting 100x100xb), the automatic fault detection mode is run instead. fault status clear (d1) write a 1 to this bit while writing 0 to bits d5, d3, and d2 to return all fault status bits (d[7:2]) in the fault status register to 0. note that bit d2 in the fault register, and subsequently bit d0 in the rtd lsb register may be set again immediately after resetting if an over/undervoltage fault persists. the fault status clear bit d1, self-clears to 0. 50/60hz (d0) this bit selects the notch frequencies for the noise rejection filter. write 0 to this bit to reject 60hz and its harmonics; write 1 to this bit to reject 50hz and its harmonics. note: do not change the notch frequency while in auto conversion mode. table 3. fault-detection cycle control bits x = dont care d3 d2 configuration register write (binary) write action read meaning 0 0 xxxx00xxb no action fault detection finished 0 1 100x010xb fault detection with automatic delay automatic fault detection still running 1 0 100x100xb run fault detection with manual delay (cycle 1) manual cycle 1 still running; waiting for user to write 11 1 1 100x110xb finish fault detection with manual delay (cycle 2) manual cycle 2 still running maxim integrated
MAX31865 rtd-to-digital converter 14 rtd resistance registers (01h?02h) two 8-bit registers, rtd msbs and rtd lsbs, contain the rtd resistance data. the data format is shown in table 4 . the data format is simply the 15-bit ratio of rtd resistance to reference resistance. d0 of the rtd lsbs register is a fault bit that indicates whether any rtd faults have been detected. table 4. rtd resistance registers definition table 5. rtd resistance-data relationship note: d0 (fault) is assumed to be 0. register rtd msbs (01h) register rtd lsbs (02h) register bit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 rtd resistance data msb lsb fault bit weighting 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 decimal value 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 r rtd /r ref binary hex decimal rtd msbs (01h) rtd lsbs (02h) rtd msbs (01h) rtd lsbs (02h) 0.025 0000 0110 0110 0110b 06h 66h 819 0.125 0010 0000 0000 0000b 20h 00h 4096 0.25 0100 0000 0000 0000b 40h 00h 8192 0.50 1000 0000 0000 0000b 80h 00h 16,384 0.75 1100 0000 0000 0000b c0h 00h 24,576 0.999 1111 1111 1111 1110b ffh feh 32,767 maxim integrated
MAX31865 rtd-to-digital converter 15 table 6. fault threshold registers definition table 7. fault status register definition fault threshold registers (03hC06h) the high fault threshold and low fault threshold registers select the trip thresholds for rtd fault detection. the results of rtd conversions are compared with the values in these registers to generate the fault (d[7:6]) bits in the fault status register. the rtd data registers, high fault threshold registers, and low fault threshold registers all have the same format. the rtd high bit in the fault status register is set if the rtd resistance register value is greater than or equal to the value in the high fault threshold register. the por value of the high fault threshold register is ffffh. the rtd low bit in the fault status register is set if the rtd resistance value is less than or equal to the value in the low fault threshold register. the por value of the low fault threshold register is 0000h. fault status register (07h) the fault status register latches any detected fault bits; writing a 1 to the fault status clear bit in the configuration register returns all fault status bits to 0. serial interface the MAX31865 supports spi modes 1 and 3. four pins are used for spi-compatible communications: sdo (serial-data out), sdi (serial-data in), cs (chip select), and sclk (serial clock). sdi and sdo are the serial- data input and output pins for the devices, respectively. the cs input initiates and terminates a data transfer. sclk synchronizes data movement between the master (microcontroller) and the slave (MAX31865). the serial clock (sclk), which is generated by the microcontroller, is active only when cs is low and dur- ing address and data transfer to any device on the x = dont care x = dont care register high fault threshold msb (03h) register high fault threshold lsb (04h) register low fault threshold msb (05h) register low fault threshold msb (06h) register bit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 rtd resistance data msb lsb x bit weighting 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 decimal value 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 d7 d6 d5 d4 d3 d2 d1 d0 rtd high threshold rtd low threshold refin- > 0.85 x v bias refin- < 0.85 x v bias (force- open) rtdin- < 0.85 x v bias (force- open) overvoltage/ undervoltage fault x x maxim integrated
MAX31865 rtd-to-digital converter 16 spi bus. the inactive clock polarity is programmable in some microcontrollers. the MAX31865 automatically accommodates either clock polarity by sampling sclk when cs becomes active to determine the polarity of the inactive clock. input data (sdi) is latched on the internal strobe edge and output data (sdo) is shifted out on the shift edge (see table 8 and figure 5 ). there is one clock for each bit transferred. address and data bits are transferred in groups of eight, msb first. address and data bytes address and data bytes are shifted msb-first into the serial-data input (sdi) and out of the serial-data output (sdo). any transfer requires the address of the byte to specify a write or a read, followed by one or more bytes of data. data is transferred out of the sdo for a read opera tion and into the sdi for a write operation. the address byte is always the first byte transferred after cs is driven low. the msb (a7) of this byte determines whether the following byte is written or read. if a7 is 0, one or more byte reads follow the address byte. if a7 is 1, one or more byte writes follow the address byte. for a single-byte transfer, 1 byte is read or written and then cs is driven high (see figure 6 and figure 7 ). for a multiple-byte transfer, multiple bytes can be read or written after the address has been written (see figure 8 ). the address continues to increment through all memory locations as long as cs remains low. if data continues to be clocked in or out, the address loops from 7fh/ffh to 00h/80h. invalid memory addresses report an ffh value. attempting to write to a read-only register results in no change to that registers contents. table 8. function table note: cpha bit polarity must be set to 1. * cpol is the clock polarity bit that is set in the control register of the microcontroller. ** sdo remains at high impedance until 8 bits of data are ready to be shifted out during a read. figure 5. serial clock as a function of microcontroller clock polarity (cpol) mode cs sclk sdi sdo disable reset high input disabled input disabled high impedance write low cpol = 1*, sclk rising data bit latch high impedance cpol = 0, sclk falling read low cpol = 1, sclk falling x next data bit shift** cpol = 0, sclk rising shift shift internal strobe internal strobe cpol = 1 cpol = 0 sclk sclk note: cpol is a bit that is set in the microcontroller?s control register. cs cs maxim integrated
MAX31865 rtd-to-digital converter 17 figure 6. spi single-byte read figure 7. spi single-byte write figure 8. spi multibyte transfer a7 sclk sdi sdo high-z d7 d6 d5 d4 d3 d2 d1 d0 a6 a5 a4 a3 a2 a1 a0 cs a7 sclk sdi sdo high-z a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 cs address byte sclk sdi write read sdi sdo data byte 0 data byte 0 data byte 1 data byte n data byte 1 data byte n address byte cs maxim integrated
MAX31865 rtd-to-digital converter 18 drdy the drdy output goes low when a new conversion result is available in the rtd data registers. when a read- operation of the rtd data registers completes, drdy returns high. applications information for operation in noisy environments, a filter capacitor may be placed across the rtdin+ and rtdin- inputs. after an overvoltage or undervoltage fault, after a fault detection cycle, or after enabling v bias , always allow for the settling time of the input filter before restarting the adc. a delay time of at least five time constants plus an additional 1ms (for the protection devices to stabilize) is recommended to achieve specified accuracy. converting rtd data register values to temperature the ratiometric adc conversion results found in the rtd data registers can be converted to temperature with a few calculations. first, the resistance of the rtd needs to be determined with the following equation: r rtd = (adc code x r ref )/2 15 figure 9. drdy operation sdo rtd data rtd data address rtd register contents drdy cs sdi conversion n conversion n+1 conversion n+2 maxim integrated
MAX31865 rtd-to-digital converter 19 adc code = 15-bit adc results from rtd data registers (01hC02h) r ref = resistance of the reference resistor once the resistance of the rtd is known, the well- defined resistive properties of the selected rtd can be used to determine temperature by either calculations or lookup tables. in the typical case of a pt100 rtd with a 400 i high precision low drift reference resistor, table 9 shows examples of temperature and resistance values with the corresponding adc code results. table 9. temperature example for pt100 with 400 i r ref temperature (c) rtd resistance ( ) rtd data reg (01h - 02h) (hex) adc code (dec) adc code/32-256 (c) -200 18.52 0bdah 1517 -208.59 -175 29.22 12b4h 2394 -181.19 -150 39.72 196ch 3254 -154.31 -125 50.06 200ah 4101 -127.84 -100 60.26 2690h 4936 -101.75 -75 70.33 2d04h 5762 -75.94 -50 80.31 3366h 6579 -50.41 -40 84.27 35eeh 6903 -40.28 -30 88.22 3876h 7227 -30.16 -20 92.16 3afch 7550 -20.06 -10 96.09 3d7eh 7871 -10.03 0 100.00 4000h 8192 0.00 10 103.90 4280h 8512 10.00 20 107.79 44fch 8830 19.94 30 111.67 4778h 9148 29.88 40 115.54 49f2h 9465 39.78 50 119.40 4c6ah 9781 49.66 60 123.24 4ee0h 10096 59.50 70 127.08 5154h 10410 69.31 80 130.90 53c6h 10723 79.09 90 134.71 5636h 11035 88.84 100 138.51 58a4h 11346 98.56 110 142.29 5b12h 11657 108.28 120 146.07 5d7ch 11966 117.94 130 149.83 5fe4h 12274 127.56 140 153.58 624ch 12582 137.19 150 157.33 64b0h 12888 146.75 160 161.05 6714h 13194 156.31 170 164.77 6974h 13498 165.81 180 168.48 6bd4h 13802 175.31 190 172.17 6e30h 14104 184.75 200 175.86 708ch 14406 194.19 225 185.01 7668h 15156 217.63 250 194.10 7c3ah 15901 240.91 maxim integrated
MAX31865 rtd-to-digital converter 20 table 9. temperature example for pt100 with 400 i r ref (continued) detecting rtdin+ cable faults in the 3- and 4-wire rtd connection configuration, a broken or disconnected rtdin+ cable results in an unbiased adc+ input into the MAX31865. this causes unpredictable adc conversion results, which can be influenced by pcb layout, external circuit noise, and ambient temperature. this cable fault condition can go undetected depending upon the values set in the fault threshold registers. if this condition is of interest, add a 10m resistor from the rtdin+ pin to the bias pin. doing so results in a full-scale rtd resistance measurement if the rtdin+ lead is broken or disconnected. decoding rtd and cable fault conditions an open rtd element or a short across the rtd element are detected on every conversion based on the resistance data. an open rtd element results in a full- scale reading. set the threshold for open rtd element detection using the high fault threshold registers. if the conversion result is greater than or equal to the threshold value, the rtd high bit in the fault status register is set at the end of the conversion. an open rtd element can also be detected on demand by testing for v refin- > 0.85 x v bias . a shorted rtd element produces a conversion result near zero. set the threshold for shorted rtd detection in the low fault threshold registers. table 10 , table 11 , and table 12 summarize how rtd and cable faults are detected for 2-, 3-, and 4-wire setups and provide a description for the most common cause. fault status bits are latched until the fault clear bit in the configuration register is set. this allows intermittent faults to be captured. power-supply decoupling to achieve the best results when using the device, decouple the v dd and dvdd power supplies with a 0.1f capacitor. use a high-quality, ceramic, surface- mount capacitor if possible. surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high- frequency response for decoupling applications. temperature (c) rtd resistance ( ) rtd data reg (01h - 02h) (hex) adc code (dec) adc code/32-256 (c) 275 203.11 81feh 16639 263.97 300 212.05 87b6h 17371 286.84 325 220.92 8d64h 18098 309.56 350 229.72 9304h 18818 332.06 375 238.44 989ah 19533 354.41 400 247.09 9e24h 20242 376.56 425 255.67 a3a2h 20945 398.53 450 264.18 a914h 21642 420.31 475 272.61 ae7ah 22333 441.91 500 280.98 b3d4h 23018 463.31 525 289.27 b922h 23697 484.53 550 297.49 be64h 24370 505.56 maxim integrated
MAX31865 rtd-to-digital converter 21 table 10. decoding rtd faults for 2-wire setups when fault bit in rtd data lsb register = 1 table 11. decoding rtd faults for 3-wire setups when fault bit in rtd data lsb register = 1 fault status bit set description of possible cause condition detected description of resulting data d7 open rtd element measured resistance greater than high fault threshold value full scale d6 shorted rtd element measured resistance less than low fault threshold value near zero rtdin+ shorted low d5 open rtd v refin - > 0.85 x v bias full scale rtdin+ shorted high indeterminate rtdin- shorted high indeterminate d4 rtdin- shorted low v refin - < 0.85 x v bias (force- open) appear to be valid d3 rtdin- shorted low v rtdin- < 0.85 x v bias (force- open) appear to be valid rtdin+ shorted low near zero d2 overvoltage or undervoltage fault any protected input voltage >v dd or 0.85 x v bias full scale force+ shorted high and connected to rtd force+ unconnected indeterminate force+ shorted high and not connected to rtd rtdin- shorted high d4 rtdin- shorted low v refin - < 0.85 x v bias (force- open) appear to be valid d3 force+ shorted low v rtdin - < 0.85 x v bias (force- open) near zero rtdin+ shorted low and connected to rtd rtdin- shorted low appear to be valid d2 overvoltage or undervoltage fault any protected input voltage >v dd or < gnd1 indeterminate maxim integrated
MAX31865 rtd-to-digital converter 22 table 12. decoding rtd faults for 4-wire setups when fault bit in rtd data lsb register = 1 fault status bit set description of possible cause condition detected description of resulting data d7 open rtd element measured resistance greater than high fault threshold value full scale rtdin+ shorted high and not connected to rtd force+ shorted high and connected to rtd d6 rtdin+ shorted to rtdin- measured resistance less than low fault threshold value near zero rtdin+ shorted low and not connected to rtd rtdin- shorted high and not connected to rtd force+ shorted low d5 open rtd element v refin - > 0.85 x v bias full scale force+ shorted high and connected to rtd force- unconnected indeterminate force+ unconnected force+ shorted high and not connected to rtd force- shorted high and not connected to rtd force- shorted high and connected to rtd force- shorted low and not connected to rtd d4 force- shorted low and connected to rtd v refin - < 0.85 x v bias (force- open) indeterminate rtdin- shorted low and connected to rtd appear to be valid d3 force+ shorted low v rtdin - < 0.85 x v bias (force- open) near zero rtdin+ shorted low and connected to rtd rtdin- shorted low and connected to rtd appear to be valid rtdin- shorted low and not connected to rtd force- shorted low d2 overvoltage or undervoltage fault any protected input voltage >v dd or < gnd1 indeterminate maxim integrated
MAX31865 rtd-to-digital converter 23 typical application circuits (continued) MAX31865 bias refin+ dvdd v dd gnd1 gnd2 dgnd refin- drdy isensor sdi sclk host interface cs sdo n.c. force- r ref rtd r cable r cable 0.1f v dd force+ force2 rtdin+ rtdin- c i * r cable 0.1f v dd 3-wire sensor connection MAX31865 bias refin+ dvdd v dd gnd1 gnd2 dgnd refin- drdy isensor sdi sclk host interface cs sdo n.c. force- r ref rtd 0.1f v dd force+ force2 rtdin+ rtdin- c i * *c i = 10nf for 1k rtd 100nf for 100 rtd 0.1f v dd 2-wire sensor connection maxim integrated
MAX31865 rtd-to-digital converter 24 ordering information package information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. *ep = exposed pad. part temp range pin-package MAX31865atp+ -40 c to +125 c 20 tqfn-ep* MAX31865atp+t -40 c to +125 c 20 tqfn-ep* package type package code outline no. land pattern no. 20 tqfn-ep t2055+5 21-0140 90-0010 maxim integrated
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 25 ? 2012 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 10/12 initial release MAX31865 rtd-to-digital converter

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